The manufacturing of various electronic devices (including but not limited to for example, microprocessors, storage devices, graphic processors, analog to digital converters, digital to analog converters, signal processors, image processors, etc.) now requires the cost-effective production of very small structures and features, e.g., structures and features having a characteristic dimension at the micrometer or nanometer size scale. This manufacturing includes the formation of electrically conductive material(s) (e.g., aluminum, copper, etc.) and electrically insulating dielectric material(s) (e.g., silicon dioxide, silicon nitride, etc.) on or as part of a substrate. Moreover, the electrically conductive material(s) are typically separated by regions of dielectric material(s) so as to define electrical elements (e.g., transistors, capacitors, etc.) and interconnections between such electrical elements.
Many electronic devices include multiple layers of electrical elements and/or interconnections (e.g., interconnect layer(s)). Each interconnect layer comprises conductive material(s) separated by dielectric material(s). As an example, a first layer of dielectric material is formed on an electrically conductive material (first conductive layer). A second layer of dielectric material is formed on the first layer of dielectric material. Trenches (e.g. lines) are formed in the second layer of dielectric material, and vias (e.g., holes) are then formed in the first layer of dielectric material. Electrically conductive material is subsequently formed in the trenches and vias so as to electrically connect the now electrically conductive trenches (second conductive layer) to the electrically conductive material (first conductive layer) through the now electrically conductive vias.
High performance microelectronic devices are obtained by the continuous downscaling of their critical dimensions. However, this downscaling also leads to an increase in RC-delay and cross talk which adversely affects the performance of the device. To reduce this delay, the dielectric constant of the low k-material that insulates the interconnect wiring has to decrease. The decrease in dielectric constant will also lead to a lower power consumption of the device. A key factor to decrease the k-value drastically is introducing porosity into the electrically insulating dielectric material because air has a dielectric constant of 1 which is the lowest value that can be obtained. However, a huge problem with porous dielectric materials and especially for mesoporous dielectric materials (pore sizes from 2 to 50 nm) is that moisture, chemical solvents and/or metal particles can diffuse into the pores leading to an high increase in k-value and leakage current.
Therefore, pore sealing technologies are essential for the implementation of mesoporous structures as low-k materials. A known sealing method is a plasma treatment of the porous low-k material which creates a densification at the surface of the low-k material. However, plasma treatments can also cause a change in structure, composition and porosity of the material. Moreover, mesoporous films are sensitive for diffusion of reactive components which means that plasma treatment might affect the quality of the bulk porous material as well. A known alternative is the deposition of a dense layer via chemical vapor deposition (CVD) or atomic layer deposition (ALD). Pore sizes smaller than 2 nm can be sealed by plasma treatment, CVD and ALD. Among the drawbacks of these techniques are the diffusion of the barrier into the pores and the fact that current dielectric barriers have a relatively high dielectric constant. Molecular self-assembly is a technique that can be used to produce very small structures having a dimension at the nanometer size scales. Molecular self-assembly can be used to produce a variety of material formations, such as molecular monolayers (often referred to as self-assembled monolayers, or SAMs), molecular multilayers and nanostructures (e.g., nanotubes, nanowires). For example, a SAM has been used as a barrier layer (replacing the deposited barrier layer) that inhibits diffusion of copper into a dielectric material. However, this SAM inhibits copper diffusion into SiO2 or fluorinated SiO2, both of which are non-porous dielectric materials. Porous dielectric materials provide additional challenges to inhibiting diffusion because the pores of porous dielectric materials provide another diffusion pathway for foreign material (e.g., barrier layer material, copper) into the dielectric material. SAMs have been proposed for use as bulk diffusion barrier layers, especially for use with dense dielectric materials such as silicon dioxide. There is a need in the art for preventing diffusion of foreign material through the exposed pores of porous dielectrics.
However advanced nano-electronics are presently developing materials for 22 nm technology nodes and beyond. In this case the dielectric constant of the interlayer dielectrics must be smaller than 2.0. Such ultra low-k materials generally have a porosity exceeding 50% and a pore size of 3 nm or more. Here the existing sealing technologies are no longer efficient.
Therefore is desirable to have a method to at least partially seal the pores of a porous material, in particular a porous low-k dielectric material, without the drawbacks of the state of the art. More specifically, new strategies for sealing pores larger than 3 nm are urgently needed.